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By Dylan McGrath, EE Times
March 21, 2006
http://www.eetimes.com/news/design/products/showArticle.jhtml?articleID=183701527
SAN FRANCISCO — Analog IC EDA tool provider Anasift Technology
Inc. Tuesday (March 21) announced the beta release of the AASpice
simulation tool, which is targeted for high-performance analog
ICs used in a number of applications.
According to Anasift (San Jose, Calif.), AASpice is integrated
with the company's Ampso transistor-level analog optimization
system.
According to J.J. Hsu, Anasift founder and president, AASpice
is a stand-alone analog simulator specifically fine-tuned to integrate
with Ampso to achieve faster and accurate verification to reduce
the iterations of tedious analog design optimization.
"Anasift's Ampso with the integration of AASpice provides
a great value to its customers because customers don't need extra
Spice licenses to run analog optimization," Hsu said. "Besides
the saving in cost for analog optimization, AASpice is also tailored
for users to easily specify various design constraints of analog
optimization."
Anasift said AASpice offers better convergence and performance
than existing Spice simulators. The product is fully compatible
with HSpice and Spice models and netlists, the company said, and
supports Bsim3, Bsim4, SOI, Hisim, Mos9 and other models.
Anasift's products are designed to fit into analog design flows
offered by top-tier EDA vendors Cadence Design Systems Inc., Synopsys
Inc. and Mentor Graphic Corp.
Copyright
© 2006 CMP Media, LLC
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