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By Dylan McGrath, EE Times
March 27, 2006
http://www.eetimes.com/news
SAN FRANCISCO — Analog IC EDA tool provider Anasift Technology
Inc. Monday (March 27) rolled out the beta release of Ampso-OADFM,
a design-for-manufacturing (DFM) optimization tool for analog
design.
Ampso-OADFM, incorporating the engine of Anasift's Ampso analog
optimization tool, targets the transistor-level optimization of
DFM for analog building circuits, including opamps, analog buffers,
comparators, voltage regulators, line drivers/receivers, trans-impedance
amplifiers and others, Anasift (San Jose, Calif.) said. The tool
aims to provide analog design optimization with better manufacturability
and yield, the company said.
"With Ampso analog optimization engine embedded inside,
Ampso-OADFM can optimize analog circuits to maintain high analog
performances, and also take care of all possible characteristic
fluctuations due to the uncertainty or variation of manufacture
process," said J.J. Hsu, Anasift founder and president, in
a statement.
Hsu noted that DFM has been a hot topic in the IC industry, but
that much of the attention has been focused on digital ICs. But
more than 70 percent of system-on-chip (SoC) designs are mixed-signal,
Hsu said, and analog circuits are more sensitive to process variation
and prone to defects.
Ampso-OADFM is designed to fit into existing analog design flows
from Cadence Designs Systems Inc., Synopsys Inc. and Mentor Graphics
Corp., Anasift said. Pricing information was not disclosed.
Last week, Anasift announced the beta release of its AASpice
simulation tool, which is targeted for high-performance analog
ICs used in a number of applications.
Copyright
© 2006 CMP Media, LLC
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