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NE Asia Online
April 3, 2006
http://neasia.nikkeibp.com/dailynewsdetail/003869
April 3, 2006 -- Anasift Technology Inc has announced the beta
release of AMPSO-OADFM, an optimization tool of analog design
for manufacturability. AMPSO-OADFM, incorporating the engine of
the company's analog optimization tool AMPSO, is targeted at the
transistor-level optimization of analog design for manufacturability
for all kinds of analog building circuits including opamps, analog
buffers, comparators, voltage regulators, line drivers/receivers,
trans-impedance amplifiers, and other analog building blocks,
or the analog characteristics of small digital cells.
The device is claimed to be the best of its kind as an analog
optimization tool; it is aimed at providing analog design optimization
with better manufacturability and yield for analog building circuits.
It can optimize an analog amplifier used in an 8-bit 205MHz samples
per second ADC in less than one day in one regular Intel CPU,
and requires no SPICE license.
"With AMPSO analog optimization engine embedded inside,
AMPSO-OADFM can optimize analog circuits to maintain high analog
performance, and also take care of all possible characteristic
fluctuations due to the uncertainty or variation of manufacture
process. DFM has attracted much attention recently in the industry.
Current DFM topics are mostly focused on the digital ICs only.
However the facts that more than 70% of SoC designs are mixed-signal,
and analog circuits are more sensitive to process variation and
prone to produce defects of mixed-signal IC functions make people
realize that the key problem in DFM of mixed-signal SoC is more
in the analog part than in digital," said Dr J J Hsu, founder
and president of Anasift.
The device takes a SPICE netlist or AMPSO optimization file as
input. It accepts typical SPICE model files. It can optimize analog
designs to meet design specifications across statistical variations
of manufacture process corners to improve manufacturability and
to insure high yield and accurate silicon implementation. It is
designed to fit into existing Cadence Mentor Graphics and Synopsys
analog design flows.
(NE Asia Online)
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© 2006 CMP Media, LLC
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